1. Technical Field of the Invention
The present invention relates to a frequency divider capable of dividing a frequency in a wide range at high frequencies and a PLL circuit that utilizes the frequency divider and, more specifically, to a frequency divider using an injection locked frequency divider (ILFD) and a PLL circuit that utilizes the frequency divider.
2. Related Art
In recent years, the frequency band utilized for wireless communication is increasing and in accordance, it is necessary to increase the frequency of a clock output from a VCO (voltage controlled oscillator) of a PLL circuit provided within a device. Usually, the reference frequency is much lower than the clock frequency output from the VCO and it is necessary to reduce the frequency by dividing the clock frequency, and therefore, a frequency divider is used. When the VCO generates a clock of tens of GHz, it is difficult to configure a frequency divider by an ordinary digital circuit and as a prescaler configured to divide a clock output from the VCO into a frequency at a certain level, an analog frequency divider is used. It is possible to implement an analog frequency divider by, for example, a current mode logic frequency divider or injection locked frequency divider (ILFD). A current mode logic frequency divider has a wide locking region; however, power consumption is large. The present invention relates to an injection locked frequency divider.
FIG. 1 is a diagram showing an outline of a configuration of an injection locked frequency divider.
An injection locked frequency divider (ILFD) 10 has an oscillation circuit 11 and a locked signal generating circuit 12. The oscillation circuit 11 is a self-oscillation circuit and capable of changing the oscillation frequency in accordance with a locked signal input from the locked signal generating circuit 12. The locked signal generating circuit 12 generates a locked signal to oscillate the oscillation circuit 11 at a target frequency of a frequency-divided signal from an input oscillation signal (clock) Nf0 and injects the locked signal into the oscillation circuit 11.
FIG. 2A and FIG. 2B are diagrams showing a model of an injection locked frequency divider, wherein FIG. 2A shows a model configured to perform division by N and FIG. 2B shows a model configured to perform division by 2.
As shown in FIG. 2A, in this model, a signal (clock) of a reference frequency f0 passes through a transistor having nonlinear transconductance and generates higher harmonics. When nothing is injected into the oscillation circuit, these harmonics are attenuated by a low-pass filter (LPF) within the oscillation circuit and many of them are attenuated. However, when a locked signal is injected, these harmonics are mixed with the injected locked signal and a number of additional harmonics are generated. If one of these harmonics has a frequency close to the self-oscillation frequency of the oscillator and enough power, the frequency of the oscillator is pulled into the frequency and locks to the frequency. This action is the direct conversion in which an (N−1)th harmonic is mixed with the locked signal of an Nth harmonic to generate a harmonic having a frequency close to the fundamental frequency of the oscillator and locks thereto. As N increases, the (N−1)th harmonic becomes weaker, and therefore, the locking range becomes narrower. Further, the level of a specific harmonic of the injection locked frequency divider cannot be controlled because the generation process thereof is not linear and affected by a number of factors. Due to this, the locking range becomes narrower and the injection power necessary for a specific division ratio is limited.
As described above, the locking range of the injection locked frequency divider and the necessary injection power differ in accordance with the division ratio and in general, in the case of division by 2, the locking range is wide and the injection power is small. FIG. 2B shows a model of a divide-by-2 injection locked frequency divider.
For the injection locked frequency divider, various kinds of configuration are known and one of them is a circuit that utilizes a ring oscillator (ring-shaped oscillation circuit) in which a plurality of delay elements is connected in the shape of a ring. The ring oscillator has a configuration in which a plurality of delay elements is connected so that the output signal of the previous stage is input as the input signal of the subsequent stage, the output signal of the final stage is input as the input signal of the initial stage, and relative to the input signal of the initial stage, the input signal from the final stage to the initial stage is reversed. The ring oscillator is a widely-known circuit.
FIG. 3A and FIG. 3B are diagrams showing a configuration example of an injection locked frequency divider that utilizes a two-stage ring oscillator, wherein FIG. 3A shows a block diagram and FIG. 3B shows a specific circuit example in which a delay element is implemented by a differential buffer circuit. An example in which a MOS transistor is used is shown, however, it is not limited to this.
In the injection locked frequency divider that utilizes a ring oscillator, by applying a locked signal to part of the delay element that performs the oscillation action to generate harmonics, the ring oscillator is caused to oscillate at a frequency in correspondence to the locked signal. The injection locked frequency divider includes the direct system in which a locked signal is applied to the part that outputs an oscillation signal, the parallel system in which a locked signal is applied to a differential pair provided in parallel to a differential pair that performs the oscillation action, and the system in which a locked signal is applied to the common connection node that connects in common the output node of a differential pair and the node on the opposite side. In general, the transistor that forms a differential pair is called a tail transistor and here, the system in which a locked signal is applied to the common connection node is called a tail system and the common connection node is called a tail.
FIG. 3A shows an injection locked frequency divider that utilizes a tail system ring oscillator. Delay elements DL1 and DL2 are a differential buffer (inverter) and a positive output out+ and a negative output out− of the delay element DL1 of the first stage are connected to a negative input in− and a positive input in+ of the delay element DL2 of the second stage and the positive output out+ and the negative output out− of the delay element DL2 of the second stage are connected to the positive input in+ and the negative input in− of the delay element DL1 of the first stage. Due to this, the output of the second stage corresponding to the input of the first stage is reversed and returned to the input of the first stage again, and thereby, the ring oscillator oscillates. The oscillation frequency of the ring oscillator is determined by the delay times of the two delay elements DL1 and DL2 if there is no injection of a locked signal.
As shown in FIG. 3B, the delay element DL1 is a differential buffer and an input signal is input to the gates of two NMOS transistors forming a differential pair and from the drains of the two NMOS transistors, an output signal is output. The sources of the two NMOS transistors are connected to the common node, that is, the tail, and the common node (tail) is grounded via source transistors M1 and M2. To the gates of the source transistors M1 and M2, a DC bias voltage is applied via a resistor.
In the injection locked frequency divider of FIG. 3A, to the gate of the source transistor M1 of the delay element DL1 of the first stage, a capacitor is further connected and to the other terminal of the capacitor, a locked signal RF2+ is applied. On the other hand, to the gate of the source transistor M2 of the delay element DL2 of the second stage, a capacitor is also connected, however, the other terminal of the capacitor is grounded. The locked signal RF2+ is a signal having a frequency 2f0, twice the frequency f0 of a frequency-divided signal output from the injection locked frequency divider. In other words, the injection locked frequency divider of FIG. 3 is a divide-by-2 frequency divider configured to divide the input oscillation signal having the frequency 2f0 into the frequency-divided signal having the frequency f0.
The frequency having a tendency to lock of the injection locked frequency divider is determined by the circuit characteristics of the injection locked frequency divider and affected by variations in processes etc. As described above, the locking range and the necessary injection power of the injection locked frequency divider are different depending on the division ratios and there used to be such a problem that it is difficult to stably operate in the state of being locked in a particularly high division ratio. In contrast to this, the model of a divide-by-2 injection locked frequency divider as shown in FIG. 2B has a wide locking range and small injection power generally. P. Mayr, C. Weyers, and U. Langmann (“A 90 GHz 65 nm CMOS Injection-Locked Frequency Divider”, IEEE International Solid-State Circuits Conference, Feb 2007, pp. 198-199) describe that two divide-by-2 injection locked frequency dividers are connected in series to perform and division by 4 (×4).